1. Field of the Invention
The present invention relates to gain controlling circuitry, and more particularly, to a gain controller for digitally controlling the gain of an input signal using switched capacitors.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional gain controller for controlling the gain of an input signal using switched capacitors. The gain controller of FIG. 1 includes feedback capacitors CF1 and CF2, an operational amplifier 10, input capacitors CI1 and CI2, and MOS transistors MN1 through MN7 which operate as switches.
FIG. 2 shows waveforms of first and second control clock signals Q1 and Q2 for controlling the opening and closing of the MOS transistors MN1 through MN7 shown in FIG. 1, which operate as the switches. The clock signals Q1 and Q2 of FIG. 2 are applied to MOS transistors MN1 through MN7 as shown in FIG. 1. Specifically, Q1 is used to control MOS a transistors MN3 through MN7, and Q2 is used to control MN1 and MN2. It is noted that the falling edge of the first control clock signal Q1 does not overlap the rising edge of the second control clock signal Q2. This is to prevent the MOS transistors MN1 and MN2 and the MOS transistors MN3 through MN7 from being simultaneously turned on.
The gain controller shown in FIG. 1 operates in two modes. Namely, the gain controller operates in a sampling mode when the first control clock signal Q1 is at a logic xe2x80x9chighxe2x80x9d level and operates in an amplifying mode when the second control clock signal Q2 is at the logic xe2x80x9chighxe2x80x9d level.
Charge amounts QI1 and QI2 charged to the input capacitors CI1 and CI2, respectively, in the sampling mode are equal to the sums Qf1 and Qf2 of charge amounts charged to the input capacitors CI1 and CI2 and the feedback capacitors CF1 and CF2, respectively, in the amplifying mode. When the capacitance of the input capacitors CI1 and CI2 is CI and the capacitance of the feedback capacitors CF1 and CF2 is CF, the following relationship is established between the difference VINTxe2x88x92VINC between input voltages VINT and VINC and the difference VOUTTxe2x88x92VOUTC between output voltages VOUTT and VOUTC.                                           V            OUTT                    -                      V            OUTC                          =                                            C              I                                      C              F                                ⁢                      (                                          V                INT                            -                              V                INC                                      )                                              (        1        )            
A feedback factor is 1/xcex2 in the amplifying mode. Here, xcex2 is a feedback gain value, which is represented as follows.                     β        =                              C            F                                              C              I                        +                          C              F                                                          (        2        )            
As the above-mentioned feedback factor 1/xcex2 increases, the operating speed of the gain controller shown in FIG. 1 is reduced. Therefore, in order to increase the operating speed of the gain controller, the value of xcex2 defined by Equation 2 must be increased.
It is assumed that the MOS transistors MN1 and MN3 and the input capacitor CI1 shown in FIG. 1 constitute a cell. A plurality of cells are connected to the negative input terminal of the operational amplifier 10 in parallel. Also, it is assumed that the MOS transistors MN2 and MN4 and the input capacitor CI2 constitute another cell. A plurality of cells are connected to the positive input terminal of the operational amplifier 10 in parallel. In order to select desired cells among the cells connected An parallel, an externally generated digital gain control signal is used. Accordingly, the value of the gain CI/CF shown in Equation 1 can be changed.
In the conventional gain controller, the digital gain control signal is used in order to change the value of CI/CF. Only one cell is selected. The input capacitance of the capacitor included in the selected cell is previously set so as to obtain a desired value of CI/CF. Namely, when the gain CI/CF of the difference VINTxe2x88x92VINC is to be controlled as a CI/CF in the conventional gain controller, corresponding two cells, which include the capacitor having the capacitance a*CFxe2x80x2 (CFxe2x80x2 is the capacitance of CF), are to be selected in response to the digital gain control signal among the plurality of cells connected to the positive and negative input terminals of the operational amplifier 10 in parallel.
For example, it is assumed that the capacitance of the feedback capacitor CF is set to be CO and that first through fourth cells are connected to the negative input terminal of the operational amplifier 10 in parallel. Also, it is assumed that fifth through eighth cells are connected to the positive input terminal of the operational amplifier 10 in parallel and that the capacitor included in the first cell and the capacitor included in the fifth cell have the capacitance CO. Also, it is assumed that the capacitor included in the second cell and the capacitor included in the sixth cell have capacitance 2CO and that the capacitor included in the third cell and the capacitor included in the seventh cell have capacitance 4CO. Also, it is assumed that the capacitor included in the fourth cell and the capacitor included in the eighth cell have capacitance 8CO and that the gain of the difference is controlled by the digital gain control signal of two bits. In the conventional gain controller, in order to control the gain of the difference to be xe2x80x981xe2x80x99, a digital gain control signal xe2x80x9800xe2x80x99 is received and the capacitors included in the first and fifth cells are selected. Also, in the conventional gain controller, in order to control the gain of the difference to be xe2x80x982xe2x80x99, a digital gain control signal xe2x80x9801xe2x80x99 is received and the capacitors included in the second and sixth cell are selected. In the conventional gain controller, in order to control the gain to be xe2x80x984xe2x80x99, a digital gain control signal xe2x80x9810xe2x80x99 is received and the capacitors included in the third and seventh cells are selected. Also, in the conventional gain controller, in order to control the gain to be xe2x80x988xe2x80x99, a digital gain control signal xe2x80x9811xe2x80x99 is received and the capacitors included in the fourth and eighth cells are selected. In this case, the feedback gain xcex2 of the gain controller shown in FIG. 1 becomes 1/16. This is because CF is CO and CI is 15CO in Equation 2. Also, in this case, the feedback factor is xe2x80x9816xe2x80x99.
FIG. 3 is a bode plot for describing the operation of the gain controller shown in FIG. 1. The horizontal axis denotes frequency and the vertical axis denotes open loop gain represented by dB. The operational amplifier 10 shown in FIG. 1 has the frequency characteristic 20 as shown in FIG. 3. The operation frequency of the gain controller shown in FIG.1 is fxe2x88x923dB, which is a point where the feedback factor 1/xcex2 (illustrated by reference numeral 22) of the gain controller shown in FIG. 1 crosses the frequency characteristic 20 of the gain controller. Here, the operation frequency fxe2x88x923dB increases as the feedback factor 1/xcex2 decreases. Also, as the operation frequency fxe2x88x923dB increases, the operating speed of the gain controller increases. However, in the conventional gain controller shown in FIG. 1, the feedback factor is xe2x80x9816xe2x80x99. Accordingly, the operating speed is not as fast.
In particular, when the gain must be controlled to be precise over a wide range, only two corresponding cells must be selected and the capacitances of the capacitors included in the selected cells must be increased. Therefore, the entire sampling capacitance, for example, CO+2CO+4CO+8CO increases. Accordingly, the feedback gain is exponentially reduced. As the feedback gain is exponentially reduced, the feedback factor increases. The operating speed is significantly reduced as the feedback factor increases as shown in FIG. 3.
It is an object of the present invention to provide a gain controller using switched capacitors, capable of very quickly controlling the gain of an input signal with low power consumption.
To achieve the above object, there is provided a gain controller which is operable in a sampling mode or an amplifying mode and which controls the gain of an analog input signal. The gain controller of the invention includes an operational amplifier, input capacitors, a feedback capacitor and a plurality of switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected in parallel to the input side of the operational amplifier. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and an externally applied predetermined digital gain control signal.
In one embodiment, each of the switches comprises at least one transistor.
In one embodiment, the gain of the operational amplifier is expressed as a ratio of an input capacitance to the capacitance of the feedback capacitor. The input capacitance is the sum of the capacitances of the input capacitors that are connected to the input signal.
In one embodiment, the digital gain control signal is generated so that the desired input capacitance is determined by the combination of the capacitances of corresponding capacitors among the input capacitors.
The gain controller can be included in a charge-coupled interface system of an image processing system. The interface system can include a charge-coupled device for generating image data, i.e., photographing an image. A correlated double sampler (CDS) samples and holds the photographed image and outputs the sampled and held image. The system also includes an analog-to-digital converter. The gain controller differentially inputs the output of the CDS and controls the gain of the output of the CDS in response to the digital gain control signal. The digital gain control signal is a digital signal processed result corresponding to the level of a digital signal. The analog-to-digital converter converts an analog input signal whose gain is controlled by the gain controller into the digital signal.